FIG. 27 shows an example of this kind of optical transmission system (PON system). In FIG. 27, reference numeral 401 denotes an OLT (station-side apparatus); 402, an optical splitter; 403, an ONU (subscriber-side apparatus); 404, an external network (host apparatus); 405, an optical fiber laid between each ONU 403 and the optical splitter 402; 406, an optical fiber laid between the optical splitter 402 and the OLT 401; and 407, an optical transmission channel (PON section) between the OLT 401 and the ONUs 403. The OLT 401 transfers frames between the external network 404 and the plurality (M) of ONUs 403 connected via the optical splitter 402.
In this PON system, upstream frames transmitted as optical signals from the plurality of ONUs 403 are bundled by the optical splitter 402 and then transferred to the OLT 401. The OLT 401 controls the transmission timings of the upstream frames transmitted from the plurality of ONUs 403 so the upstream frames transmitted from the ONUs 403 do not collide with each other on the optical fiber 406, and performs processing of transferring upstream frames from the ONUs 403 to the external network 404 and processing of transferring a downstream frame from the external network 404 to each ONU 403.
FIG. 28 shows an example of the OLT 401. The OLT 401 includes an optical transceiver 408, a frame reproduction circuit 409, and a PON control circuit 410. The optical transceiver 408 performs electro-optical conversion of a downstream frame to each ONU 403, and photoelectric conversion of an upstream frame from each ONU 403. The frame reproduction circuit 409 performs processing for reproducing a frame from an electrical signal, such as FEC (Forward Error Correction) and encryption. Note that the input/output portion of the optical transceiver 408 is called a PON port (communication port). The OLT 401 shown in FIG. 28 is an OLT with a 1-PON port arrangement.
FIG. 29 shows an example of the PON control circuit 410. The PON control circuit 410 includes a data frame processing circuit 411 and a control frame processing circuit 412. The data frame processing circuit 411 processes data frames between the ONUs 403 and the external network 404. The control frame processing circuit 412 processes control frames between the ONUs 403 and the OLT 401. The upstream frame from each of the ONUs 403 includes an upstream data frame and an upstream control frame, and the downstream frame from the external network 404 includes a downstream data frame.
The data frame processing circuit 411 performs buffering processing, bridge processing, and the like. The control frame processing circuit 412 generates a downstream control frame by performing processing for establishing/managing a link with each ONU 403 and DBA (Dynamic Bandwidth Allocation) processing for controlling the transmission timings of the upstream frames, and transmits the generated downstream control frame to each ONU 403. That is, while the data frame is transferred upstream and downstream, the control frame is turned back in the control frame processing circuit 412 and transmitted to each ONU 403.
In this PON system, to reduce the total cost of the PON system, there is proposed a system (multiport PON system) in which one OLT accommodates a plurality of PON ports (see, for example, non-patent literature 1). In the multiport PON system, it is possible to increase the number of accommodated ONUs for one OLT, thereby reducing the system cost for one ONU.
FIG. 30 shows an example of an OLT in a related multiport PON system. An OLT 401 in this multiport PON system has N (N is an integer of 2 or more) PON ports, and includes N optical transceivers 408 (408-1 to 408-N) equal in number to the PON ports, N frame reproduction circuits 409 (409-1 to 409-N), and N PON control circuits 410 (410-1 to 410-N).
The OLT 401 in this multiport PON system can accommodate M ONUs 403 for one PON port, and accommodate (N×M) ONUs 403 at most. A control frame processing circuit 412 in each PON control circuit 410 has resources (hardware resources, CPU processing capability) capable of performing link establishment/management processing and DEA processing in accordance with the number of the M ONUs 403 or the number of logical IDs (LLIDs) assigned as identifiers to the M ONUs 403. The maximum number (M) of accommodated ONUs for one PON port is determined based on the resources (processing capability) of the PON control circuit 410.
Note that in FIGS. 28 to 30, reference numeral 413 denotes an upstream data frame; 414, a downstream data frame; 415, an upstream control frame; and 416, a downstream control frame.
However, in an actual multiport PON system, the number of ONUs to be accommodated or the number of LLIDs for each PON port hardly reaches the limited value (M) of the number. Thus, there are unused resources, thereby deteriorating the use efficiency of the PON control circuit. Also, it is wasteful in terms of electric power to use the PON control circuit with low use efficiency.